Advance Packaging

through-wafer interconnectsSTS work with a number of customers involved in developing innovative Advanced Packaging solutions, providing a range of process capabilities which are used at specific steps in the manufacturing route.

By using our in-depth knowledge of the MEMS market and packaging challenges faced by MEMS manufacturers, STS has provided key process steps which may be utilised in a wider range of packaging applications.

These include:

  • PECVD of encapsulating layers
  • Dry isotropic etch of sacrificial layers
  • Through-wafer interconnects
  • Controlled profile silicon etch

Key challenges

  • Reducing die size and increased packing
  • Reducing cost of packaging
  • Maintaining protective atmosphere for device
  • CMOS-compatibility

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