Wafer Geometry and Its Impact on Yield

By Dan Lopez,
Senior Director of Marketing, KLA-Tencor
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Dan Lopez is leading the marketing efforts for
KLA-Tencor’s newly acquired ADE Division, a leader
in bare wafer surface metrology.

While immersion lithography is enabling the resolution of smaller line widths, depth of focus continues to decrease with each technology node. Depth of focus — the distance range within which lithographic imaging of semiconductor critical dimensions will be sharply in focus — comes into play if a portion of a semiconductor surface is higher or lower than the rest. If so, that portion can be out of focus. Exceeding depth of focus windows can cause numerous lithography defects, affecting IC device yield.

Looking to advanced design specifications, wafers which meet the ITRS roadmap for flatness will nevertheless consume 40% to 50% of available immersion depth of focus, through site surface variation. Flatness variation of mere nanometers in these areas will put focus at risk, since other processing factors such as stage repeatability, and chuck flatness may also contribute to defocus. Beyond 45nm designs, this window gets smaller still. One of the challenges facing the industry moving forward will be producing wafers that are flat enough to maintain depth of focus, yet cost-effective.

Wafer flatness
Since wafer flatness consumes the largest part of the available focus budget, controlling flatness has the greatest effect on the available focus window. High quality site flatness (SFQR) measurements ensure that wafer topography is not consuming excessive portions of the process window. Full-wafer interferometry measurements are available today
which overcome the measurement instability of other site flatness metrology approaches.

Figure 1. A 300 mm wafer’s SFQR map from KLA-Tencor’s
WaferSight 2 system. A large number of sites have more than 45nm
peak-to-valley, with tilt removed within the site.

Nanotopography
Repeatable measurement of nanotopography will be essential for 45nm node designs, where the ITRS roadmap specifies nanotopography of 11nm or less. Nanotopography may cause
thickness variations in photoresist, and result in post-CMP thickening of films in nanotopographic valleys or over-thinning of peaks. Such features can result in IC defects, which may limit yield or affect reliability.

Figure 2. 2D profile of nanotopography, with relative
effects on film uniformity

Edge roll-off
Defined as departures from flatness occurring within one to five millimeters of the edge of a wafer, edge roll-off is an area of particular challenge in wafer processing. Process performance can be difficult to control near the wafer edge, due to changes in the polishing pad pressure, issues arising from film tension, and other factors. Consequently, it is common to see more die defocus and CMP issues at the edge than in the center. Control of edge roll-off — especially at one millimeter from the edge — could enhance die yield per wafer in economically significant ways.

Control of wafer geometry — site flatness, nanotopography, and edge roll-off — can improve focus control, planarization, and edge die yield for advanced design rules. In order to realize these improvements, the most accurate and precise wafer geometry measurements must be relied upon.

To see how the WaferSight 2 can increase your yield, please go to:
www.kla-tencor.com/08wafersightUS