Wafer Edge Yield By Frank Burkeen
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Senior Product Marketing Director at KLA-Tencor
Frank.Burkeen@kla-tencor.com With the scaling of 300mm production and the development of sub-90nm device technology, defect sources from the wafer’s edge have become a major concern. The most demanding process integration challenges, due to increased device and stack complexity, frequently lead to defect control problems in this most difficult inspection area. Thin, fragile films produced with exotic dielectrics and other advanced materials cause difficulties when deposited over residues in the high stress wafer edge region. The introduction of immersion lithography adds to the potential for poorly adhering films to flake off and cause yield loss. Additionally, any loose flakes or film peel-offs along the wafer apex-bevel regions can transfer to the process tools and scanners, causing long tool-down events. These issues, in combination with the need to realize 300mm yield entitlement, are leading to increased focus on the wafer edge. 
Figure 1: VisEdge CV300’s multi-channel detection system detects significant film flaking and peeling on the wafer edge. Historically, wafer edge inspection has focused on mechanical damage, like chips and cracks, or other physical damage. Widely available technologies have been used to construct inspection systems sensitive to this category of edge defect. These systems have established a production use case for OQC in wafer manufacturing. However, the IC manufacturer is most interested in process integration and production related issues on the wafer’s edge, often quite different from actual silicon damage. Newly emerging is the need for an inspection solution specifically targeted at film-related issues resulting from various process integration steps, such as deposition, CMP and etch. These defects can include delaminated films or “blisters”, post processing residues from CMP or etch, or process integration issues caused by interfacial stress or poor adhesion. These defect sources generate particulates from the wafer edge in subsequent processing steps. This debris can migrate onto the printed area of the wafer, causing yield loss, or onto the process tool chuck, possibly bringing a critical tool down. Currently, there are two general technology approaches for inspecting the wafer edge. The first is a line scan laser that produces a scatter signal and uses thresholding to pick up potential defects, then returns to these points and takes pictures with a digital camera. Although well-proven in wafer manufacturing, this system is designed to find scattering defects such as chips, cracks, and particles. Scatter-based detection tends to miss film defects and residues, severely limiting the value of these tools for IC manufacturing. 
Figure 2: Multi-sensor imaging, particularly specular imaging, can distinguish between open and closed blisters on the wafer edge region (popped blisters appear white, un-popped appear black). The second technology involves visible light imaging of the wafer’s edge with CCD-based digital microscopy. This “camera-based” has two significant and fundamental drawbacks. One drawback is that the capability to image and detect defects is dependent upon the curvature and shape of the wafer’s edge. At the magnification level necessary to see 2-5μm defect sources, the depth of field severely limits the “in-focus” field of view. This forces the use of multiple cameras to accommodate complete wafer edge coverage. The second drawback and biggest limitation for use of CCD-based edge inspection in process control is the lack of accurate, reliable automatic defect classification (ADC). Discrete wafer images must be “stitched” together and traditional color- and contrast-based classification routines are unreliable due to strong edge background variation. CCD technology can provide working pictures of a wafer’s edge, but so far the lack of robust ADC has prevented production use of these tools. Edge defectivity data must be quantified, accurate, and reliable before becoming useful as a process monitoring parameter. The growing need to control defect sources at the wafer edge have resulted in a requirement for inspection in this region. As fabs develop a baseline on edge defect sources and impact on overall yield through monitoring and control strategies, a fully automated inspection system for the wafer edge is imperative. To learn more about wafer edge inspection, go to: www.kla-tencor.com/edgeNov2 | 
